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Curriculum vitae                                               


        29, Mirador, Irvine CA 92612

            Tel: (949)-7250152 (Home)

                   (949)-4284210 (work)

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Date of birth:          January 19th, 1972

Place of Birth:          Pavia, Italy

Nationality:               Italian


Studies:                  @ Maturita’ Scientifica, Liceo Copernico, Pavia, July 1990 60/60 (High School)

                           @ Degree in electrical engineering (09/1990-03/1996)

                               University of Pavia, Italy 110/110 Summa Cum Laude (Master)

                                 Average marks during degree in electronic engineering: 29/30  

                            @M.B.A. University of California, Irvine (09/1999-06/2002)


Thesis:                  “Architectural study and project of basic building blocks for a  

                               2 Ghz 2 V CMOS frequency synthesizer"

                                Tutor: Prof. Rinaldo Castello


Publications:                ESSCIRC (European Solid State Circuit Conference), England 1997

                                “A Low Voltage CMOS Downconversion Mixer for RF applications”,  

                                           Valentina Della Torre, Matteo Conta, Francesco Svelto, Rinaldo Castello  

                                ESSCIRC, 2000 

                                “GSM/DCS tranceiver with integrated synthesiser”

                       Rahul Magoon, Akbar Ali, Matteo Conta et al

                                    ISSCC, 2001 

                                “A 27 mW fully integrated GPS radio in 035um CMOS

                                Farbod Behbahani, Hamid Firouzouki, Matteo Conta et al


Work:                          Position: RF Integrated Circuit Design Engineer IV, RF IC Design,

                               Conexant Systems, Newport Beach, CA 92660, (August 1996, October 2000)

                               Position: Senior Staff Engineer 

                               Valence Semiconductor, Irvine, CA 92612, (October 2000, present)


Projects:          @ 20-100Mhz fully integrated PLLs for clock generation in 0.5um,

                                  0.35um, 0.25um CMOS technology (production parts).

                              @ 600Mhz Fully Programmable Dual Loop Frequency Synthesizer in 0.5um,

                                   0.35um CMOS  technology for CDMA cellular phones (production part).

                               @ 2Ghz/400Mhz BiCMOS Fully Programmable Dual Frequency Synth

                                   for GSM cellular phones (production part).

                               @ Transmit path of GSM/DCS tranceiver

                               @ Test chips for RF LC VCOs, prescalers, IQ generators, low jitter PLLs …  

                               @ GPS Frequency Synthesizer in 0.35um,

                                   0.35um CMOS  technology (production part).

                                @WLAN 802.11 Tranceiver in 0.18um CMOS

                        system analysis from OFDM Matlab to chip specs

                                    responsible for SX, TX paths and top level chip integration


Courses:                       @ RF IC Design for Wireless Communication Systems, Lausann 1-5 July 1996.

       @ 1997 IEEE International Solid State Circuit Conference, San Francisco.  

    @ A lot of internal Conexant Talent Advancement Program courses


Patents:           Author of 6 US patents in the area of low noise low power phase lock loops.


Skills:                           High frequency testing; CAD: CADENCE, HSPICE, ELDO, SPECTRE RF,

                                      MENTORGRAPHIC, MATLAB, MATHCAD, MATHEMATICA, UNIX,



Languages:                   Italian: mother tongue; English, French: understood, spoken, read.


Periods Abroad:       1980-1982 France; 1996-present California, USA.